The present invention relates to timing analysis programs, timing analysis apparatuses, and timing analysis methods, and for example, relates to a timing analysis program, a timing analysis apparatus, and a timing analysis method used for semiconductor integrated circuits including various types of transistors having different thresholds.
In recent years, the speeding-up of semiconductor devices has been advancing. As a result, timing restrictions imposed on the setup time and hold time have become very severe. Therefore, at a design stage of semiconductor devices, a timing analysis for verifying timing restrictions is performed as one process of the design stage. An example of generation method of parameters used for this timing analysis is disclosed in Japanese Unexamined Patent Application Publication No. 2007-133497. This publication discloses a technology in which the characteristic distributions of a semiconductor integrated circuit are extracted by a mathematical analysis using polynomial expressions on the basis of the variation distributions of process sensitivity parameters. In the technology disclosed in this publication, variation distributions of the characteristics of a semiconductor integrated circuit are effectively extracted by this method.